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SUNNYVALE, Calif.--(BUSINESS WIRE)--Aug. 20, 2001--Continuing to tackle designer productivity issues, Synplicity, Inc. (Nasdaq:SYNP), a leading supplier of software for the design and verification of semiconductors, today announced it has automated its Certify(TM) verification synthesis software to speed the development of FPGA-based ASIC prototypes. The software can now perform many time consuming tasks automatically, including partitioning, gated-clock conversion and pin multiplexing, shaving days or weeks off of the prototyping process. Featuring Synplicity's new Quick Partitioning Technology, the Certify software now provides designers with the capability to automatically partition an ASIC design onto multi-FPGA custom boards for the development of ASIC prototypes. Additionally, Synplicity has enhanced the Certify software's automatic gated-clock conversion and Certify pin multiplexing (CPM) features to increase the speed and performance of ASIC prototypes.

``Synplicity has consistently developed software solutions that help enable designers to innovate and broaden their design goals,'' said Andy Haines, vice president of marketing for Synplicity. ``By increasingly automating our software and making it easier to use, we have made it possible for most designers to become proficient users of our solutions and obtain high quality of results in the least amount of time. With the development of new automated features, including our Quick Partitioning Technology, we are continuing our goal of providing designers with leading-edge design solutions and speed time-consuming design tasks.''

First introduced in May 1999, the Certify software is the industry's first registered transfer level (RTL) prototyping solution that enables designers to create functional hardware prototypes of their ASIC design at the RTL, prior to ASIC synthesis. Verification at this early stage of design results in a dramatic increase in productivity and enables faster time to market. Today, the Certify software is being used by dozens of users to solve their ASIC verification needs.

Jerry Worchel, president, inSearch Research, said, ``Traditionally, prototyping an ASIC design onto an FPGA board has been a time-consuming process that could only be performed by very experienced design engineers, severely hindering design team resources. By further automating its Certify software to perform many of the tedious tasks involved in prototype development, Synplicity has enabled design engineers, regardless of their prototyping experience, to quickly and easily take advantage of the verification benefits FPGA-based prototypes offer.''

Quick Partitioning Technology

With the addition of the Quick Partitioning Technology in the Certify 5.0 software, Synplicity has automated one of the most time-consuming processes in prototyping -- partitioning. Traditionally, a designer needed to use the Certify software's guided interactive partitioning feature to partition a design manually. Following the designer's manual effort, the software would provide users with feedback to assist with any decision-making regarding the design, such as I/O usage and area usage. With the Quick Partitioning Technology, a user can optionally set goals for area and I/O usage on the FPGAs in the prototype, then run the Certify software to automatically partition the design onto a custom board.

Early benchmark results show typical ASIC designs that are run through the Certify software using Quick Partitioning Technology are able to be automatically partitioned onto a custom board, often in under a minute. The same design manually partitioned onto a custom board by an experienced designer required several hours or more, on average. On very complex designs, the savings in partitioning time can be days. Additionally, when design changes are made during the verification process with the prototype, the functional changes can be made directly to the original RTL and automatically re-partitioned resulting in even more time savings.

The new Certify software provides greater flexibility for designers trying to meet specific design requirements by offering both automated and manual partitioning capabilities, or any combination of the two. This feature enables a designer to either manually place timing-critical blocks in specific FPGAs and then let the Certify software automatically partition the rest of the design, or let the Certify software automatically partition the whole design before manually partitioning parts of the design.

Additional Automation-Specific Enhancements to the Certify Software

Continuing to speed the prototyping process, Synplicity has enhanced a key ASIC conversion feature already in the Certify software, the ability to recognize additional gated-clock elements in an ASIC when they are converted into an FPGA. In addition to the logic gate elements previously recognized in the clock tree, the software can now also detect clock trees with inferred and instantiated memories, inferred and instantiated latches, instantiated registers, shift registers, state machines, and counters. By developing these unique algorithms that enable the Certify software to recognize complex gated-clock elements, Synplicity has eliminated the traditionally time-consuming task of manually converting gated-clock elements.

Additionally, the Certify software's Certify pin multiplexing capabilities have been enhanced to provide users with the flexibility to choose more CPM implementations including off-chip control modules, enabling a wider choice in pin multiplexing between FPGAs. The CPM feature allows a designer to time divide signals between pins and share I/Os on a device in order to conserve pins. The additional CPM functionality in the Certify software provides designers with greater flexibility as to what type of time division multiplexing to use in a design.

In automating these tasks, Synplicity delivers an easy to use product that can enable a significant savings in design team resources. Using this product, engineers who are not experts in prototyping or engineers who are not familiar with the design that is being prototyped, are able to quickly verify an ASIC with very little effort. Also, because of this automation and ease of use, a design team is not required to use its most experienced engineers to create a functional ASIC prototype.

Pricing and Availability

The Certify 5.0 software is available now for $115,000 for Windows NT, Windows 2000 and UNIX (Solaris & HP) operating systems. Current Certify customers on maintenance will be upgraded at no additional cost.

About the Certify Software

Leveraging Synplicity's core synthesis and partitioning technologies, the Certify product is designed to enable designers to create functional hardware prototypes of their design prior to ASIC synthesis. This approach enables higher performance and productivity than gate-level partitioning approaches, which require multiple iterations to achieve a suitable partitioning of the devices. It also enables faster time-to-market, especially for the one-million-gate-plus ASIC/SoC designs used for multimedia and communications applications. Synplicity believes that prototypes defined by the Certify product will enable extensive verification allowing ASIC designers to perform the following tasks at- or near-system speed: hardware/software co-verification; algorithm development and verification; verification of intellectual property, either cores or library elements; system software development and debugging, verification of system-level protocol compatibility and early system/product development with FPGAs.

About Synplicity

Synplicity, Inc. (Nasdaq:SYNP) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in next-generation networking and communications hardware and other electronic devices. The company leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs) and system-on-chip (SoC) integrated circuits. Synplicity's fast, easy-to-use products offer extremely high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of the end of June 30, 2001, Synplicity employed over 250 people in its 16 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif.

The specific features, functionality and release timing of any new products or new versions of current products remain at the sole discretion of Synplicity, Inc., and Synplicity does not make any warranty as to when or if specific features, functionality or releases may occur.

Forward-looking Statement

This press release contains forward-looking statements. These statements relate to future events and involve known and unknown risks, uncertainties and other factors that may cause Synplicity's actual product performance or achievements to differ materially from those expressed or implied by the forward-looking statements. In some cases, you will be able to identify forward-looking statements by terminology such as ``anticipates,'' ``intends,'' ``may,'' ``will,'' ``expects,'' ``potential,'' ``continue'' or the negative of these terms or other comparable terminology. Forward-looking statements are only predictions and the actual events or results may differ materially, particularly with respect to the continued acceptance of Synplicity's existing products and the successful introduction and widespread market acceptance of Synplicity's new products. For additional information and considerations regarding the risks faced by Synplicity, see its Registration Statement on Form S-1 and Form 10-K for the fiscal year ended December 31, 2000, as well as periodic reports on Forms 10-Q as filed with the Securities and Exchange Commission. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee future results, levels of activity, performance or achievements. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy and completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement.

Note to Editors: Synplicity is a registered trademark and Certify is a trademark of Synplicity, Inc. All other brands or products are the trademarks or registered trademarks of their owners.

SYB-099

     Synplicity, Inc., Sunnyvale
     Brian Caslis, 408/215-6000 (Reader)
     caslis@synplicity.com
        or
     Tsantes & Associates
     Steve Gabriel, 408/369-1500 (Press)
     steve@tsantes.com